1. Field of the Invention
This invention relates generally to binary III-V compound NPN transistors and, more particularly, to a gallium arsenide (GaAs) transistor having a self-aligned base enhancement to emitter region and an improved method of applying metal to the emitter region.
2. Background Art
Semiconductor integrated circuits include a plurality of transistors, diodes, and the like formed by creating a variety of doped regions in a semiconductor wafer substrate. These regions are formed by performing a number of operations, for example, epitaxial growth, diffusions, ion implantations, etching processes, etc. These operations normally are carried out by a number of masking steps. The devices are then interconnected by a conductive metallization layer to form the desired circuit function.
Self-alignment of a transistor may be defined as the ability to define the edge of the extrinsic base of a transistor in close proximity to the edge of the active emitter-base junction in a manner that does not use photolithography techniques to define that spacing. Many self-aligned silicon NPN transistor structures and methods for the fabrication thereof have been proposed in the past that are able to provide reliable devices having a high yield in manufacture. However, self-aligned GaAs bipolar transistor structures and methods for the fabrication thereof have heretofore not been known. Furthermore, metal contact widths have been limited by minimum masking dimensions, thus requiring the emitter or collector regions on the semiconductor surface to have an area greater than the minimum masking width possible so as to prevent the metal from shorting to the base.
Thus, a method of fabricating a GaAs transistor having a self-aligned base enhancement to emitter region and an improved method of applying a metal contact having a width less than minimum masking dimensions is needed.